Advances in semi-conductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple cores and multiple logical processors present on individual integrated circuits. An integrated circuit typically comprises a single processor die, where the processor die may include any number of cores or logical processors.
As an example, a single integrated circuit may have one or multiple cores. The term core usually refers to the ability of logic on an integrated circuit to maintain an independent architecture state, where each independent architecture state is associated with at least some dedicated execution resources. As another example, a single integrated circuit or a single core may have multiple logical processors for executing multiple software threads, which is also referred to as a multi-threading integrated circuit or a multi-threading core. Multiple logical processors usually share common data caches, instruction caches, execution units, branch predictors, control logic, bus interfaces, and other processor resources, while maintaining a unique architecture state for each logical processor.
The ever increasing number of cores and logical processors on integrated circuits enables more software threads to be executed. However, the increase in the number of software threads that may be executed simultaneously has created problems with synchronizing data shared among the software threads. One common solution to accessing shared data in multiple core or multiple logical processor systems comprises the use of locks to guarantee mutual exclusion across multiple accesses to shared data. However, the ever increasing ability to execute multiple software threads potentially results in false contention and a serialization of execution.
Another solution is using transactional execution to access shared memory to execute instructions and operate on data. Often transactional execution includes speculatively executing a grouping of a plurality of micro-operations, operations, or instructions. During speculative execution of a transaction by a processor, core, or thread, the memory locations read from and written to are tracked to see if another processor, core, or thread accesses those locations. If another thread invalidly alters those locations, the transaction is restarted and it is re-executed from the beginning. Transaction execution potentially avoids deadlock associated with traditional locking mechanisms, provides error recovery, and makes fine-grained synchronization possible.
Previously, transactional execution has been implemented either fully in hardware, which requires complex and expensive logic but is relatively fast, or software, which is less expensive and more robust but incurs significant performance overhead in certain situations. For example, software transactional memory is able to efficiently execute nested transactions, but a significant amount of execution time and resources are wasted due to the instrumentation of memory accesses inside a transaction. The instrumentation is to ensure that different transaction accesses disjointed memory locations. For example, when a single thread is running, in certain cases, software transactional memory incurs a 2-3× performance overhead compared to a traditional lock based implementation. In software implemented systems typically the greatest overhead is found in tracking load accesses to locations and validating locations accessed before committing a transaction.
In contrast, in a hardware only transactional memory system, a transaction may be executed faster, as software is not needed to track each access; however, transaction size as well as functionality is sacrificed, because of the expensive and complex circuitry/logic required. Some recent research proposals have focused on forms of hybrid transactional execution where a transaction is first executed in hardware and, upon failure, executed in software. However, some performance features that are achieved through software still have to incur the overhead associated with executing the transaction in hardware first, before the advantages are realized.